RM0440 Rev 4 1405/2126
RM0440 General-purpose timers (TIM15/TIM16/TIM17)
1445
Note: The state of the external I/O pins connected to the complementary tim_ocx and tim_ocxn
channels depends on the tim_ocx and tim_ocxn channel state and AFIO registers.
Table 299. Output control bits for complementary tim_ocx and tim_ocxn channels with break
feature (TIM15)
Control bits Output states
(1)
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit tim_ocx output state tim_ocxn output state
1X
X0 0
Output Disabled (not driven by the timer: Hi-Z)
tim_ocx=0
tim_ocxn=0
00 1
Output Disabled (not driven
by the timer: Hi-Z)
tim_ocx=0
tim_ocxref + Polarity
tim_ocxn=tim_ocxref XOR
CCxNP
01 0
tim_ocxref + Polarity
tim_ocx=tim_ocxref XOR
CCxP
Output Disabled (not driven by
the timer: Hi-Z)
tim_ocxn=0
X1 1
tim_ocxref + Polarity +
dead-time
Complementary to tim_ocxref
(not OCREF) + Polarity + dead-
time
10 1
Off-State (output enabled
with inactive state)
tim_ocx=CCxP
tim_ocxref + Polarity
tim_ocxn=tim_ocxref XOR
CCxNP
11 0
tim_ocxref + Polarity
tim_ocx=tim_ocxref xor
CCxP
Off-State (output enabled with
inactive state)
tim_ocxn=CCxNP
0
0
X
XX
Output disabled (not driven by the timer: Hi-Z)
1
00
0 1 Off-State (output enabled with inactive state)
Asynchronously: tim_ocx=CCxP, tim_ocxn=CCxNP
Then if the clock is present: tim_ocx=OISx and
tim_ocxn=OISxN after a dead-time, assuming that OISx and
OISxN do not correspond to tim_ocx and tim_ocxn both in
active state
10
11
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.
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