General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1300/2126 RM0440 Rev 4
1. Configure TIM_mstr master mode to send its Output Compare 1 Reference
(tim_oc1ref) signal as trigger output (MMS=100 in the TIM_mstr_CR2 register).
2. Configure the TIM_mstr tim_oc1ref waveform (TIM_mstr_CCMR1 register).
3. Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the
TIM_slv_SMCR register).
4. Configure TIM_slv in gated mode (SMS=101 in TIM_slv_SMCR register).
5. Reset TIM_mstr by writing ‘1 in UG bit (TIM_mstr_EGR register).
6. Reset TIM_slv by writing ‘1 in UG bit (TIM_slv_EGR register).
7. Initialize TIM_slv to 0xE7 by writing ‘0xE7’ in the TIM_slv counter (TIM_slv_CNT).
8. Enable TIM_slv by writing ‘1 in the CEN bit (TIM_slv_CR1 register).
9. Start TIM_mstr by writing ‘1 in the CEN bit (TIM_mstr_CR1 register).
10. Stop TIM_mstr by writing ‘0 in the CEN bit (TIM_mstr_CR1 register).
Figure 435. Gating TIM_slv with Enable of TIM_mstr
Using one timer to start another timer
In this example, we set the enable of TIM_slv with the update event of TIM_mstr. Refer to
Figure 432 for connections. TIM_slv starts counting from its current value (which can be
non-zero) on the divided internal clock as soon as the update event is generated by
TIM_mstr. When TIM_slv receives the trigger signal its CEN bit is automatically set and the
counter counts until we write ‘0 to the CEN bit in the TIM_slv_CR1 register. Both counter
clock frequencies are divided by 3 by the prescaler compared to tim_ker_ck (f
tim_cnt_ck
=
f
tim_ker_ck
/3).
1. Configure TIM_mstr master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM_mstr_CR2 register).
2. Configure the TIM_mstr period (TIM_mstr_ARR registers).
3. Configure TIM_slv to get the input trigger from TIM_mstr (TS=00010 in the
TIM_slv_SMCR register).
4. Configure TIM_slv in trigger mode (SMS=110 in TIM_slv_SMCR register).
5. Start TIM_mstr by writing ‘1 in the CEN bit (TIM_mstr_CR1 register).
MSv62377V1
tim_ker_ck
75 00
E7
tim_mstr_CNT reset
tim_mstr_CNT
AB
tim_slv_CNT
tim_slv_CNT reset
Write TIF = 0
01 02
E9E800
TIM_mst counter enable (CEN bit)
tim_slv_CNT write
tim_slv TIF bit
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