Revision history RM0440
2116/2126 RM0440 Rev 4
49 Revision history
Table 447. Document revision history
Date Revision Changes
06-May-2019 1 Initial release.
10-Oct-2019 2
Document convention section
– Updated Table 2: Product specific features.
System architecture section
– Updated Section 2.1: System architecture replacing FMC by FSMC.
– Updated Figure 2: Memory map replacing FMC by FSMC.
Memory organization section
– Updated Table 3: STM32G4 Series memory map and peripheral register boundary
addresses
– Updated Table 2.4: Embedded SRAM SRAM2 (mapped at address 0x2000 4000).
– Updated Table 7: Flash module - 512/256/128 KB dual bank organization (64 bits
read width).
– Updated Table 8: Flash module - 512/256/128 KB single bank organization (128 bits
read width).
Power control section
– Updated Section 6.1: Power supplies.
Reset and clock control section
– Updated Figure 17: Clock tree.
Updated FMC into FSMC in:
– Section 7.4.10: AHB3 peripheral reset register (RCC_AHB3RSTR).
– Section 7.4.16: AHB3 peripheral clock enable register(RCC_AHB3ENR).
– Section 7.4.22: AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR).
System controller configuration section
– Updated Section 10.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)
bits[2:0] description.
Peripherals interconnect matrix section
– Updated Table 82: Interconnect 11 on-chip source FLTxSRC[1:0] = 01 column.
Nested vectored interrupt controller section
– Updated Table 97: STM32G4 Series vector table.
Flexible static memory controller (FSMC) section
– Updated Section 19: Flexible static memory controller (FSMC).
CORDIC co-processor (CORDIC) section
– Updated Section 17: CORDIC co-processor (CORDIC).
Analog digital converter (ADC) section
– Updated Section 21.4.33: Monitoring the internal voltage reference.
– Updated Section : Sampling time control trigger mode.
Digital analog converter (DAC) section
– Updated Section 22: Digital-to-analog converter (DAC).
Comparator section
– Updated Section 24.6.2: COMP register map.
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