High-resolution timer (HRTIM) RM0440
918/2126 RM0440 Rev 4
The burst mode controller is able to take over the control of any of the 10 PWM outputs. The
state of each output during a burst mode operation is programmed using IDLESx and
IDLEMx bits in the HRTIM_OUTxR register, as in Table 232.
Note: IDLEMx bit must not be changed while the burst mode is active.
The burst mode controller only acts on the output stage. A number of events are still
generated during the idle period:
• Output set/reset interrupt or DMA requests
• External event filtering based on Tx2 output signal
• Capture events triggered by output set/reset
During the burst mode, neither start nor reset events are generated on the
hrtim_out_sync[2:1] output, even if TxBM bit is set.
Operating mode
It is necessary to have the counter enabled (TxCEN bit set) before using the burst mode on
a given timing unit.The burst mode is enabled with BME bit in the HRTIM_BMCR register.
It can operate in continuous or single-shot mode, using BMOM bit in the HRTIM_BMCR
register. The continuous mode is enabled when BMOM = 1. The burst operation is
maintained until BMSTAT bit in HRTIM_BMCR is reset to terminate it.
In single-shot mode (BMOM = 0), the idle sequence is executed once, following the burst
mode trigger, and the normal timer operation is resumed immediately after.
The duration of the idle and run periods is defined with a burst mode counter and 2
registers. The HRTIM_BMCMPR register defines the number of counts during which the
selected timer(s) are in an idle state (idle period). HRTIM_BMPER defines the overall burst
mode period (sum of the idle and run periods). Once the initial burst mode trigger has
occurred, the idle period length is HRTIM_BMCMPR+1, the overall burst period is
HRTIM_BMPER+1.
Note: The burst mode period must not be less than or equal to the deadtime duration defined with
DTRx[8:0] and DTFx[8:0] bitfields.
The counters of the timing units and the master timer can be stopped and reset during the
burst mode operation. HRTIM_BMCR holds 6 control bits for this purpose: MTBM (master)
and TABM..TEBM for timer A..E.
When MTBM or TxBM bit is reset, the counter clock is maintained. This allows to keep a
phase relationship with other timers in multiphase systems, for instance.
When MTBM or TxBM bit is set, the corresponding counter is stopped and maintained in
reset state during the burst idle period. This allows to have the timer restarting a full period
when exiting from idle. If SYNCSRC[1:0] = 00 or 10 (synchronization output on the master
Table 232. Timer output programming for burst mode
IDLEMx IDLESx Output state during burst mode
0 X No action: the output is not affected by the burst mode operation.
1 0 Output inactive during the burst
1 1 Output active during the burst
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