Inter-integrated circuit (I2C) interface RM0440
1892/2126 RM0440 Rev 4
41.4.10 I2C_TIMINGR register configuration examples
The tables below provide examples of how to program the I2C_TIMINGR to obtain timings
compliant with the I
2
C specification. In order to get more accurate configuration values, the
STM32CubeMX tool (I2C Configuration window) must be used.
Table 380. Examples of timing settings for f
I2CCLK
= 8 MHz
Parameter
Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
10 kHz 100 kHz 400 kHz 500 kHz
PRESC 1 1 0 0
SCLL 0xC7 0x13 0x9 0x6
t
SCLL
200x250 ns = 50 µs 20x250 ns = 5.0 µs 10x125 ns = 1250 ns 7x125 ns = 875ns
SCLH 0xC3 0xF 0x3 0x3
t
SCLH
196x250 ns = 49 µs 16x250 ns = 4.0µs 4x125 ns = 500 ns 4x125 ns = 500 ns
t
SCL
(1)
~100 µs
(2)
~10 µs
(2)
~2500 ns
(3)
~2000 ns
(4)
SDADEL 0x2 0x2 0x1 0x0
t
SDADEL
2x250 ns = 500 ns 2x250 ns = 500 ns 1x125 ns = 125 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x1
t
SCLDEL
5x250 ns = 1250 ns 5x250 ns = 1250 ns 4x125 ns = 500 ns 2x125 ns = 250 ns
1. SCL period t
SCL
is greater than t
SCLL
+ t
SCLH
due to SCL internal detection delay. Values provided for t
SCL
are examples
only.
2. t
SYNC1
+
t
SYNC2
minimum value is 4 x t
I2CCLK
= 500 ns. Example with t
SYNC1
+
t
SYNC2
= 1000 ns.
3. t
SYNC1
+
t
SYNC2
minimum value is 4 x t
I2CCLK
= 500 ns. Example with t
SYNC1
+
t
SYNC2
= 750 ns.
4. t
SYNC1
+
t
SYNC2
minimum value is 4 x t
I2CCLK
= 500 ns. Example with t
SYNC1
+ t
SYNC2
= 655 ns.
Table 381. Examples of timings settings for f
I2CCLK
= 16 MHz
Parameter
Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
10 kHz 100 kHz 400 kHz 1000 kHz
PRESC 3 3 1 0
SCLL 0xC7 0x13 0x9 0x4
t
SCLL
200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 5 x 62.5 ns = 312.5 ns
SCLH 0xC3 0xF 0x3 0x2
t
SCLH
196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
t
SCL
(1)
~100 µs
(2)
~10 µs
(2)
~2500 ns
(3)
~1000 ns
(4)
SDADEL 0x2 0x2 0x2 0x0
t
SDADEL
2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 2 x 125 ns = 250 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x2
t
SCLDEL
5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
1. SCL period t
SCL
is greater than t
SCLL
+ t
SCLH
due to SCL internal detection delay. Values provided for t
SCL
are examples
only.
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