RM0440 Rev 4 1367/2126
RM0440 General-purpose timers (TIM15/TIM16/TIM17)
1445
Figure 458. Output compare mode, toggle on tim_oc1
30.4.12 PWM mode
Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per tim_ocx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
tim_ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. tim_ocx output is enabled by a
combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and
TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter).
The TIM15/TIM16/TIM17 are capable of upcounting only. Refer to Upcounting mode on
page 1353.
MSv62327V1
Counter register
‘1’
0
12 3456 7801
tim_ocxref
CCxIF
tim_ocxref
CCxIF
tim_ocxref
CCxIF
tim_ocxref
CCxIF
CCRx=4
CCRx=8
CCRx>8
CCRx=0
‘0’
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