General-purpose timers (TIM15/TIM16/TIM17) RM0440
1384/2126 RM0440 Rev 4
Figure 474. Retriggerable one pulse mode
30.4.20 UIF bit remapping
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows to
atomically read both the counter value and a potential roll-over condition signaled by the
UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.
30.4.21 Timer input XOR function (TIM15 only)
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the two input pins tim_ti1 and tim_ti2.
The XOR output can be used with all the timer input functions such as trigger or input
capture. It is useful for measuring the interval between the edges on two input signals, as
shown in Figure 475.
Figure 475. Measuring time interval between edges on 2 signals
MSv62345V1
tim_trgi
Counter
tim_ocx
MSv63068V1
tim_ti1
tim_ti2
tim_ti1 XOR tim_ti2
Counter
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