RM0440 Rev 4 537/2126
RM0440 Flexible static memory controller (FSMC)
571
6 FACCEN Set according to memory support
5:4 MWID As needed
3:2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1
Table 141. FMC_BTRx bitfields (mode D)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD HCLK cycles for read
accesses).
29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for read
accesses.
7:4 ADDHLD
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 1.
Table 142. FMC_BWTRx bitfields (mode D)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
accesses).
29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
7:4 ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 1.
Table 140. FMC_BCRx bitfields (mode D) (continued)
Bit number Bit name Value to set
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