Embedded Flash memory (FLASH) for category 3 devices RM0440
102/2126 RM0440 Rev 4
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
If the page erase is part of write-protected area (by WRP or PCROP), WRPERR is set and
the page erase request is aborted.
Bank 1, Bank 2 Mass erase (available only in dual bank mode when
DBANK=1)
To perform a bank Mass Erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the MER1 bit or MER2 (depending on the bank) in the Flash control register
(FLASH_CR). Both banks can be selected in the same operation, in that case it
corresponds to a mass erase.
4. Set the STRT bit in the FLACH_CR register.
5. Wait for the BSY bit to be cleared in the Flash status register (FLASH_SR).
Mass erase
To perform a Mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. Set the MER1 bit and MER2 in the Flash control register (FLASH_CR).
4. Set the STRT bit in the FLACH_CR register.
5. Wait for the BSY bit to be cleared in the Flash status register (FLASH_SR).
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
When DBANK=0, if only the MERA or the MERB bit is set, PGSERR is set and no erase
operation is performed.
If the bank to erase or if one of the banks to erase contains a write-protected area (by WRP
or PCROP), WRPERR is set and the mass erase request is aborted (for both banks if both
are selected).
3.3.7 Flash main memory programming sequences
The Flash memory is programmed 72 bits at a time (64 bits + 8 bits ECC).
Programming in a previously programmed address is not allowed except if the data to write
is full zero, and any attempt sets PROGERR flag in the Flash status register (FLASH_SR).
It is only possible to program double word (2 x 32-bit data).
• Any attempt to write byte or half-word sets SIZERR flag in the FLASH_SR register.
• Any attempt to write a double word which is not aligned with a double word address
sets PGAERR flag in the FLASH_SR register.
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