High-resolution timer (HRTIM) RM0440
882/2126 RM0440 Rev 4
Figure 212. Up-down mode with “greater than” comparison
Caution: The following features are not supported in up-down counting mode:
– Auto-delayed mode
– Balanced Idle
– Triggered-half mode
The capture function is supported with the following differences:
– the capture value is referred to counting start, when up-counting
– the capture value is referred to the PER event when down counting
– the bit 16 of the capture register holds the counting direction status
The counter roll-over event is defined differently in-up-down counting mode to support
various operating condition. It can be either generated:
– when the counter is equal to 0 (“valley” mode)
– when the counter reaches the period value set in the HRTIM_PERxR (“crest”
mode)
– when both conditions are met (either 0 or HRTIM_PERxR value)
This event is used for multiple purposes in the HRTIM. The generation mode (valley, crest or
both) can be programmed individually depending on the destination. Table 220 summarizes
the use cases and associated roll-over mode (xxROM[1:0]) programming bits in the
HRTIM_TIMxCR2 register.
MSv50805V1
Set on CMP1
HRTIM_CHx1
Table 220. Roll-over event destination and mode programming
Roll-over event use Programming bits
Output set/reset OUTROM[1:0]
Register content update trigger (transfer from preload to active) ROM[1:0]
IRQ and/or DMA request trigger ROM[1:0]
Burst mode clock source and /or burst start trigger BMROM[1:0]
ADC trigger (see Section : ADC post-scaler for details) ADROM[1:0]
External event filtering ROM[1:0]
Repetition counter decrement ROM[1:0]
Fault and event counter FEROM[1:0]
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