High-resolution timer (HRTIM) RM0440
908/2126 RM0440 Rev 4
Figure 232. Resynchronized timer update (TAU=1 in HRTIM_TIMBCR)
MUDIS and TxUDIS bits in the HRTIM_CR1 register allow to temporarily disable the transfer
from preload to active registers, whatever the selected update event. This allows to modify
several registers in multiple timers. The regular update event takes place once these bits
are reset.
MUDIS and TxUDIS bits are all grouped in the same register. This allows the update of
multiple timers (not necessarily synchronized) to be disabled and resumed simultaneously.
The following example is a practical use case. A first power converter is controlled with the
master, TIMB and TIMC. TIMB and TIMC must be updated simultaneously with the master
timer repetition event. A second converter works in parallel with TIMA, TIMD and TIME, and
TIMD, TIME must be updated with TIMA repetition event.
First converter
In HRTIM_MCR, MREPU bit is set: the update occurs at the end of the master timer counter
repetition period. In HRTIM_TIMBCR and HRTIM_TIMCCR, MSTU bits are set to have
TIMB and TIMC timers updated simultaneously with the master timer.
When the power converter set-point has to be adjusted by software, MUDIS, TBUDIS and
TCUDIS bits of the HRTIM_CR register must be set prior to write accessing registers to
update the values (for instance the compare values). From this time on, any hardware
update request is ignored and the preload registers can be accessed without any risk to
have them transferred into the active registers. Once the software processing is over,
MUDIS, TBUDIS and TCUDIS bits must be reset. The transfer from preload to active
registers is done as soon as the master repetition event occurs.
Second converter
In HRTIM_TIMACR, TAREPU bit is set: the update occurs at the end of the timer A counter
repetition period. In HRTIM_TIMDCR and HRTIM_TIMECR, TAU bits are set to have TIMD
and TIME timers updated simultaneously with timer A.
MSv47432V2
TIMA Counter
HRTIM_CHx1
HRTIM_CHy1
TIMB Counter
RSYNCU=1
TIMA update
RSYNCU=0
TIMB
update
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