ST STM32G474 - (Timx_Arr Not Preloaded); Figure 276. Counter Timing Diagram, Update Event When ARPE=0

Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1096/2126 RM0440 Rev 4
Figure 276. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded)
MSv62303V1
FF 36
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
00
02
03 04 05
06
0732
33
34 35
36
31
01
CEN
Auto-reload preload register
Write a new value in TIMx_ARR