RM0440 Rev 4 667/2126
RM0440 Analog-to-digital converters (ADC)
724
Combined modes summary
The Table 173 below summarizes all combinations, including modes not supported.
21.4.30 Dual ADC modes
Dual ADC modes can be used in devices with two ADCs or more (see Figure 137).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in
the ADCx_CCR register.
Four possible modes are implemented:
• Injected simultaneous mode
• Regular simultaneous mode
• Interleaved mode
• Alternate trigger mode
It is also possible to use these modes combined in the following ways:
• Injected simultaneous mode + Regular simultaneous mode
• Regular simultaneous mode + Alternate trigger mode
• Injected simultaneous mode + Interleaved mode
In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the
bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR
register are shared between the master and slave ADC: the bits in the slave ADC are
always equal to the corresponding bits of the master ADC.
To start a conversion in dual mode, the user must program the bits EXTEN[1:0], EXTSEL,
JEXTEN[1:0], JEXTSEL of the master ADC only, to configure a software or hardware
trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave
ADC are don’t care).
Table 173. Oversampler operating modes summary
Regular
Oversampling
ROVSE
Injected
Oversampling
JOVSE
Oversampler
mode
ROVSM
0 = continued
1 = resumed
Triggered
Regular mode
TROVS
Comment
1 0 0 0 Regular continued mode
1 0 0 1 Not supported
1 0 1 0 Regular resumed mode
1011
Triggered regular resumed
mode
1 1 0 X Not supported
1110
Injected and regular resumed
mode
1 1 1 1 Not supported
0 1 X X Injected oversampling
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