Flexible static memory controller (FSMC) RM0440
536/2126 RM0440 Rev 4
Figure 64. Mode D write access waveforms
The differences with mode 1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Table 140. FMC_BCRx bitfields (mode D)
Bit number Bit name Value to set
31:24 Reserved 0x000
23:22 NBLSET[1:0] As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
MSv41684V1
A[25:0]
Memory transaction
NBL[x:0]
NEx
NOE
Data driven by controller
NWE
Data bus
NBLSET
HCLK
cycles
ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1
HCLK cycles
ADDHLD
HCLK cycles
NADV
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