RM0440 Rev 4 485/2126
RM0440 CORDIC co-processor (CORDIC)
485
17.4.3 CORDIC result register (CORDIC_RDATA)
Address offset: 0x8
Reset value: 0x0000 0000
17.4.4 CORDIC register map
Refer to Section 2.2 for the register boundary addresses.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RES[31:16]
rrrrrr r r rrrrrr r r
1514131211109 8 765432 1 0
RES[15:0]
rrrrrr r r rrrrrr r r
Bits 31:0 RES[31:0]: Function result
If 32-bit format is selected (CORDIC_CSR.RESSIZE = 0) and two output values are
expected (CORDIC_CSR.NRES = 1), this register must be read twice when the RRDY flag
is set. The first read fetches the primary result (RES1). The second read fetches the
secondary result (RES2) and resets RRDY.
If 32-bit format is selected and only one output value is expected (NRES = 0), only one read
of this register is required to fetch the primary result (RES1) and reset the RRDY flag.
If 16-bit format is selected (CORDIC_CSR.RESSIZE = 1), this register contains the primary
result (RES1) in the lower half, RES[15:0], and the secondary result (RES2) in the upper
half, RES[31:16]. In this case, NRES must be set to 0, and only one read performed.
A read from this register resets the RRDY flag in the CORDIC_CSR register.
Table 116. CORDIC register map and reset value
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
CORDIC_CSR
RRDY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ARGSIZE
RESSIZE
NARGS
NRES
DMAWEN
DMAREN
IEN
Res.
Res.
Res.
Res.
SCALE
[2:0]
PRECISION
[3:0]
FUNC
[3:0]
Reset value 0 0000000 000001 0 10000
0x04
CORDIC_WDATA ARG[31:0]
Reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
0x08
CORDIC_RDATA RES[31:0]
Reset value 0000000000000000000000000 00 00000
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