General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1268/2126 RM0440 Rev 4
Figure 397. Combined PWM mode on channels 1 and 3
29.4.14 Clearing the tim_ocxref signal on an external event
The tim_ocxref signal of a given channel can be cleared when a high level is applied on the
tim_ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to
1). tim_ocxref remains low until the next update event (UEV) occurs. This function can only
be used in Output compare and PWM modes. It does not work in Forced mode.
The tim_ocref_clr_int source depends on the OCREF clear selection feature
implementation, refer to Section 29.3: TIM2/TIM3/TIM4/TIM5 implementation.
If the OCREF clear selection feature is implemented, the tim_ocref_clr_int can be selected
between the tim_ocref_clr input and the tim_etrf input (tim_etr_in after the filter) by
configuring the OCCS bit in the TIMx_SMCR register. The tim_ocref_clr input can be
selected among several tim_ocref_clr[7..0] inputs, using the OCRSEL[2:0] bitfield in the
TIMx_AF2 register, as shown in Figure 398 below.
MSv62330V1
tim_oc1ref
tim_oc2ref
tim_oc1refc
tim_oc1refc = tim_oc1ref AND tim_oc2ref
CCR1
CCR2
tim_oc1ref
tim_oc2ref
tim_oc1refc
tim1_oc1refc = tim1_oc1ref OR tim1_oc2ref
CCR1
CCR2
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