RM0440 Rev 4 1357/2126
RM0440 General-purpose timers (TIM15/TIM16/TIM17)
1445
Figure 448. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
30.4.5 Repetition counter
Section 30.4.3: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows. It is actually generated only when the repetition counter
has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N counter overflows, where N is the
value in the TIMx_RCR repetition counter register.
The repetition counter is decremented at each counter overflow.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to Figure 449). When the update event is generated by
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
MSv62304V1
F5
36
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00
02
03 04 05
06
07F1
F2
F3 F4
F5F0
01
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
Auto-reload shadow
register
F5
36
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