Power control (PWR) RM0440
246/2126 RM0440 Rev 4
6.3.5 Low-power sleep mode (LP sleep)
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power sleep mode
In Low-power sleep mode, all I/O pins keep the same state as in Run mode.
Entering the Low-power sleep mode
The Low-power sleep mode is entered from low-power run mode according Section :
Entering low power mode, when the SLEEPDEEP bit in the Cortex
®
-M4 with FPU System
Control register is clear.
Refer to Table 44: Low-power sleep for details on how to enter the Low-power sleep mode.
Exiting the Low-power sleep mode
The low-power Sleep mode is exit according Section : Exiting low power mode. When
exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-
power run mode.
Refer to Table 44: Low-power sleep for details on how to exit the Low-power sleep mode.
Table 43. Sleep
Sleep-now mode Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex
®
-M4 with FPU System Control register.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex
®
-M4 with FPU System Control register.
Mode exit
If WFI or return from ISR was used for entry
Interrupt: refer to Table 97: STM32G4 Series vector table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Section 15.3.2: Wakeup event management
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 97: STM32G4
Series vector table or Wakeup event: refer to Section 15.3.2: Wakeup
event management
Wakeup latency None
To Next Page
General
