High-resolution timer (HRTIM) RM0440
950/2126 RM0440 Rev 4
Figure 259. Burst DMA operation flowchart
Several options are available once the DMA burst is completed, depending on the register
update strategy.
If the PREEN bit is reset (preload disabled), the value written by the DMA is immediately
transferred into the active register and the registers are updated sequentially, following the
DMA transaction pace.
When the preload is enabled (PREEN bit set), there are 3 use cases:
1. The update is done independently from DMA burst transfers (UPDGAT[3:0] = 0000 in
HRTIM_TIMxCR and BRSTDMA[1:0] = 00 in HRTIM_MCR). In this case, and if it is
necessary to have all transferred data taken into account simultaneously, the user must
check that the DMA burst is completed before the update event takes place. On the
contrary, if the update event happens while the DMA transfer is on-going, only part of
the registers is loaded and the complete register update requires 2 consecutive update
events.
2. The update is done when the DMA burst transfer is completed (UPDGAT[3:0] = 0000 in
HRTIM_TIMxCR and BRSTDMA[1:0] = 01 in HRTIM_MCR). This mode guarantees
that all new register values are transferred simultaneously. This is done independently
from the counter value and can be combined with regular update events, if necessary
(for instance, an update on a counter reset when TxRSTU is set).
3. The update is done on the update event following the DMA burst transfer completion
(UPDGAT[3:0] = 0010 in HRTIM_TIMxCR and BRSTDMA[1:0] = 10 in HRTIM_MCR).
This mode guarantees both a coherent update of all transferred data and the
synchronization with regular update events, with the timer counter. In this case, if a
regular update request occurs while the transfer is on-going, it is discarded and the
effective update happens on the next coming update request.
MS32341V2
Parse
HRTIM_BDMUPR
MCR bit set?
Write data into
HRTIM_MCR
Write data into
HRTIM_MICR
Write data into
HRTIM_MCMP4
MCIR bit set?
MCMP4 bit
set?
Parse
HRTIM_BDTAUPR
TIMACR bit
set?
Write data into
HRTIM_TIMACR
Write data into
HRTIM_TIMAICR
Write data into
HRTIM_FLTAR
TIMAICR
bit set?
TIMAFLTR
bit set?
Parse
HRTIM_BDTFUPR
TIMFCR bit
set?
Write data into
HRTIM_TIMFCR
Write data into
HRTIM_TIMFICR
Write data into
HRTIM_FLTFR
TIMFICR
bit set?
TIMFFLTR
bit set?
Write access to
HRTIM_BDMADR
End of DMA burst
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