DMA request multiplexer (DMAMUX) RM0440
434/2126 RM0440 Rev 4
Note: The GNBREQ field value must be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.
Trigger overrun and interrupt
If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the status
DMAMUX_RGSR register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the
completion of the usage of the related channel of the DMA controller. Else, upon a new
detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that
is, no served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.
13.5 DMAMUX interrupts
An interrupt can be generated upon:
• a synchronization event overrun in each DMA request line multiplexer channel
• a trigger event overrun in each DMA request generator channel
For each case, per-channel individual interrupt enable, status and clear flag register bits are
available.
Table 95. DMAMUX interrupts
Interrupt signal Interrupt event Event flag Clear bit Enable bit
dmamuxovr_it
Synchronization event overrun
on channel x of the
DMAMUX request line multiplexer
SOFx CSOFx SOIE
Trigger event overrun
on channel x of the
DMAMUX request generator
OFx COFx OIE
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