RM0440 Rev 4 281/2126
RM0440 Reset and clock control (RCC)
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The LSE crystal is switched on and off using the LSEON bit in RTC domain control register
(RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best
compromise between robustness and short start-up time on one side and low-power-
consumption on the other side. The LSE drive can be decreased to the lower drive
capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the
drive capability can not be increased if LSEON=1.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the Clock
interrupt enable register (RCC_CIER).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the AHB1 peripheral
clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR). The external clock
signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while
the OSC32_OUT pin can be used as GPIO. See Figure 18.
7.2.6 LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For
more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER).
7.2.7 System clock (SYSCLK) selection
Four different clock sources can be used to drive the system clock (SYSCLK):
• HSI16 oscillator
• HSE oscillator
• PLL
The system clock maximum frequency is 170 MHz. After a system reset, the HSI16
oscillator is selected as system clock. When a clock source is used directly or through the
PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the Internal
clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and
which clock is currently used as a system clock.
To switch from low speed to high speed or from high speed to low speed system clock, it is
recommended to use a transition state with medium speed clock, for at least 1 µs.
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