RM0440 Rev 4 329/2126
RM0440 Reset and clock control (RCC)
338
7.4.27 RTC domain control register (RCC_BDCR)
Address offset: 0x90
Reset value: 0x0000 0000
Reset by RTC domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only
by RTC domain power-on reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The bits of the RTC domain control register (RCC_BDCR) are outside of the V
CORE
domain.
As a result, after Reset, these bits are write-protected and the DBP bit in the Section 6.4.1:
Power control register 1 (PWR_CR1) has to be set before these can be modified. Refer to
Section 6.1.3: Battery backup domain on page 231 for further information. These bits
(except LSCOSEL, LSCOEN and BDRST) are only reset after a RTC domain Reset (see
Section 7.1.3: RTC domain reset). Any internal or external Reset will not have any effect on
these bits.
Bits 5:4 USART3SEL[1:0]: USART3 clock source selection
This bit is set and cleared by software to select the USART3 clock source.
00: PCLK selected as USART3 clock
01: System clock (SYSCLK) selected as USART3 clock
10: HSI16 clock selected as USART3 clock
11: LSE clock selected as USART3 clock
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected as USART2 clock
01: System clock (SYSCLK) selected as USART2 clock
10: HSI16 clock selected as USART2 clock
11: LSE clock selected as USART2 clock
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK selected as USART1 clock
01: System clock (SYSCLK) selected as USART1 clock
10: HSI16 clock selected as USART1 clock
11: LSE clock selected as USART1 clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res.
LSCO
SEL
LSCO
EN
Res. Res. Res. Res. Res. Res. Res. BDRST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC
EN
Res. Res. Res. Res. Res. RTCSEL[1:0] Res.
LSE
CSSD
LSE
CSSON
LSEDRV[1:0]
LSE
BYP
LSE
RDY
LSEON
rw rw rw r rw rw rw rw r rw
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