RM0440 Rev 4 1159/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
Figure 344. Directional index sensitivity
Special first index event management
The FIDX bit in the TIMx_ECR register allows the Index to be taken only once, as shown on
the Figure 345 below. Once the first index has arrived, any subsequent index will be
ignored. If needed, the circuitry can be re-armed by writing the FIDX bit to 0 and setting it
again to 1.
Note: When FIDX = 1, the index can be issued twice (IDXF flag set) if the direction changes at
position 0 (index active).
Figure 345. Counter reset as function of FIDX bit setting
MSv45774V1
Index input
DIR bit
Counter
Counter reset
IDIR[1:0]=00
IDIR[1:0]=01
IDIR[1:0]=10
UP-counting Down-counting
MSv45775V1
Index input
Counter
Counter reset
FIDX = 0
FIDX = 1
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