ST STM32G474 User Manual

RM0440 Rev 4 317/2126
RM0440 Reset and clock control (RCC)
338
7.4.20 AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR)
Address offset: 0x68
Reset value: 0x0000 130F
Access: no wait state, word, half-word and byte access
Bit 15 SPI4EN: SPI4 timer clock enable
Set and cleared by software.
0: SPI4 timer clock disabled
1: SPI4 timer clock enabled
Bit 14 USART1EN: USART1clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 TIM8EN: TIM8 timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF + OPAMP clock enable
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF + OPAMP clock disabled
1: SYSCFG + COMP + VREFBUF + OPAMP clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res.
CRCSM
EN
Res. Res.
SRAM1
SMEN
FLASH
SMEN
Res. Res. Res.
FMACSM
EN
CORDICSM
EN
DMAMUX1
SMEN
DMA2
SMEN
DMA1
SMEN
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ST STM32G474 Specifications

General

Brand	ST
Model	STM32G474
Category	Microcontrollers
Language	English