General-purpose timers (TIM15/TIM16/TIM17) RM0440
1406/2126 RM0440 Rev 4
30.7.10 TIM15 counter (TIM15_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
30.7.11 TIM15 prescaler (TIM15_PSC)
Address offset: 0x28
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20
19 18 17 16
UIF
CPY
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r
1514131211109876543210
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit in the TIM15_ISR register.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
Non-dithering mode (DITHEN = 0)
The register holds the counter value.
Dithering mode (DITHEN = 1)
The register only holds the non-dithered part in CNT[15:0]. The fractional part is not
available.
1514131211109876543210
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (f
tim_cnt_ck
) is equal to f
tim_psc_ck
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIM15_EGR register or through
trigger controller when configured in “reset mode”).
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