RM0440 Rev 4 101/2126
RM0440 Embedded Flash memory (FLASH) for category 3 devices
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a write/erase operation is performed to the other bank (refer to Section 3.3.8: Read-while-
write (RWW) available only in dual bank mode (DBANK=1)).
The Flash erase and programming is only possible in the voltage scaling range 1. The
VOS[1:0] bits in the PWR_CR1 must be programmed to 01b.
On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the same Flash memory bank stalls the bus. The read operation proceeds correctly once
the program/erase operation has completed.
Unlocking the Flash memory
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2. Write KEY2 = 0xCDEF89AB in the FLASH_KEYR register.
Any wrong sequence locks up the FLASH_CR register until the next system reset. In the
case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
Note: The FLASH_CR register cannot be written when the BSY bit in the Flash status register
(FLASH_SR) is set. Any attempt to write to it with the BSY bit set causes the AHB bus to
stall until the BSY bit is cleared.
3.3.6 Flash main memory erase sequences
The Flash memory erase operation can be performed at page level, bank level or on the
whole Flash memory (Mass Erase). Mass Erase does not affect the Information block
(system flash, OTP and option bytes).
Page erase
To erase a page, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash
status register (FLASH_SR).
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. In dual bank mode (DBANK option bit is set), set the PER bit and select the page to
erase (PNB) with the associated bank (BKER) in the Flash control register
(FLASH_CR). In single bank mode (DBANK option bit is reset), set the PER bit and
select the page to erase (PNB). The BKER bit in the Flash control register
(FLASH_CR) must be kept cleared.
4. Set the STRT bit in the FLASH_CR register.
5. Wait for the BSY bit to be cleared in the FLASH_SR register.
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