High-resolution timer (HRTIM) RM0440
1032/2126 RM0440 Rev 4
Bit 2 TBUDIS: Timer B update disable
Refer to TAUDIS description.
Bit 1 TAUDIS: Timer A update disable
This bit is set and cleared by software to enable/disable an update event generation temporarily on
timer A.
0: Update enabled. The update occurs upon generation of the selected source.
1: Update disabled. The updates are temporarily disabled to allow the software to write multiple
registers that have to be simultaneously taken into account.
Bit 0 MUDIS: Master update disable
This bit is set and cleared by software to enable/disable an update event generation temporarily.
0: Update enabled.
1: Update disabled. The updates are temporarily disabled to allow the software to write multiple
registers that have to be simultaneously taken into account.
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