Embedded Flash memory (FLASH) for category 3 devices RM0440
104/2126 RM0440 Rev 4
bootloader. In dual bank mode (DBANK=1), perform a mass erase of the bank to
program. If not, PGSERR is set.
2. Check that no Flash main memory operation is ongoing by checking the BSY bit in the
Flash status register (FLASH_SR).
3. Check and clear all error programming flag due to a previous programming.
4. Set the FSTPG bit in Flash control register (FLASH_CR).
5. Write the 64 double words to program a row or half row. Only double words can be
programmed:
– Write a first word in an address aligned with double word
– Write the second word.
6. Wait until the BSY bit is cleared in the FLASH_SR register.
7. Check that EOP flag is set in the FLASH_SR register (meaning that the programming
operation has succeed), and clear it by software.
8. Clear the FSTPG bit in the FLASH_SR register if there no more programming request
anymore.
Note: If the flash is attempted to be written in Fast programming mode while a read operation is on
going in the same bank, the programming is aborted without any system notification (no
error flag is set).
When the Flash interface has received the first double word, programming is automatically
launched. The BSY bit is set when the high voltage is applied for the first double word, and it
is cleared when the last double word has been programmed or in case of error. The internal
oscillator HSI16 (16 MHz) is enabled automatically when FSTPG bit is set, and disabled
automatically when FSTPG bit is cleared, except if the HSI16 is previously enabled with
HSION in RCC_CR register.
The 64 double word must be written successively. The high voltage is kept on the flash for
all the programming. Maximum time between two double words write requests is the time
programming (around 2 x 25us). If a second double word arrives after this time
programming, fast programming is interrupted and MISSERR is set.
High voltage mustn’t exceed 8 ms for a full row between 2 erases. This is guaranteed by the
sequence of 64 double words successively written with a clock system greater or equal to
8MHz. An internal time-out counter counts 7ms when Fast programming is set and stops the
programming when time-out is over. In this case the FASTERR bit is set.
If an error occurs, high voltage is stopped and next double word to programmed is not
programmed. Anyway, all previous double words have been properly programmed.
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