Real-time clock (RTC) RM0440
1558/2126 RM0440 Rev 4
Note: The calendar is frozen when reaching the maximum value, and can’t roll over.
35.6.3 RTC sub second register (RTC_SSR)
Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset value: 0x0000 0000 (when BYPSHAD = 0, not affected when BYPSHAD = 1)
35.6.4 RTC initialization control and status register (RTC_ICSR)
This register is write protected. The write access procedure is described in RTC register
write protection on page 1547.
Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset value: not affected (except INIT, INITF, and RSF bits which are cleared to 0)
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
SS[15:0]
rrrrrrrrrrrrrrrr
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given
by the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RECAL
PF
r
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. INIT INITF RSF INITS SHPF
WUTW
F
ALRB
WF
ALRAW
F
rwrrc_w0rrrrr
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