Embedded Flash memory (FLASH) for category 2 devices RM0440
192/2126 RM0440 Rev 4
Instruction prefetch
The Cortex
®
-M4 fetches the instruction over the ICode bus and the literal pool
(constant/data) over the DCode bus. The prefetch block aims at increasing the efficiency of
ICode bus accesses.
Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits depending on the launched program. This 64-bits current
instruction line is saved in a current buffer, and in case of sequential code, at least two CPU
cycles are needed to execute the previous read instruction line.
Prefetch on the ICode bus can be used to read the next sequential instruction line from the
Flash memory while the current instruction line is being requested by the CPU.
Prefetch is enabled by setting the PRFTEN bit in the Flash access control register
(FLASH_ACR). This feature is useful if at least one wait state is needed to access the Flash
memory.
Figure 9 shows the execution of sequential 16-bit instructions with and without prefetch
when 3 WS are needed to access the Flash memory.
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