System window watchdog (WWDG) RM0440
1938/2126 RM0440 Rev 4
43 System window watchdog (WWDG)
43.1 Introduction
The system window watchdog (WWDG) is used to detect the occurrence of a software fault,
usually generated by external interference or by unforeseen logical conditions, which
causes the application program to abandon its normal sequence. The watchdog circuit
generates an MCU reset on expiry of a programmed time period, unless the program
refreshes the contents of the down-counter before the T6 bit becomes cleared. An MCU
reset is also generated if the 7-bit down-counter value (in the control register) is refreshed
before the down-counter has reached the window register value. This implies that the
counter must be refreshed in a limited window.
The WWDG clock is prescaled from the APB clock and has a configurable time-window that
can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications which require the watchdog to react within an
accurate timing window.
43.2 WWDG main features
• Programmable free-running down-counter
• Conditional reset
– Reset (if watchdog activated) when the down-counter value becomes lower than
0x40
– Reset (if watchdog activated) if the down-counter is reloaded outside the window
(see Figure 661)
• Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when
the down-counter is equal to 0x40.
43.3 WWDG functional description
If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the
7-bit down-counter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it
initiates a reset. If the software reloads the counter while the counter is greater than the
value stored in the window register, then a reset is generated.
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value and higher than 0x3F. The value to be stored
in the WWDG_CR register must be between 0xFF and 0xC0.
Refer to Figure 660 for the WWDG block diagram.
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