RM0440 Rev 4 1963/2126
RM0440 FD controller area network (FDCAN)
2008
Rx FIFOs
Rx FIFO 0 and Rx FIFO 1 can hold up to three elements each.
Received messages that passed acceptance filtering are transferred to the Rx FIFO as
configured by the matching filter element. For a description of the filter mechanisms
available for Rx FIFO 0 and Rx FIFO 1, see Acceptance filter. The Rx FIFO element is
described in Section 44.3.5.
When an Rx FIFO full condition is signaled by IR[RFnF], no further messages are written to
the corresponding Rx FIFO until at least one message has been read out and the Rx FIFO
Get Index has been incremented. In case a message is received while the corresponding
Rx FIFO is full, this message is discarded and interrupt flag IR[RFnL] is set.
When reading from an Rx FIFO, Rx FIFO Get Index RXFnS[FnGI] + FIFO Element Size has
to be added to the corresponding Rx FIFO start address [FnSA].
Rx FIFO Blocking Mode
The Rx FIFO blocking mode is configured by RXGFC.FnOM = 0. This is the default
operation mode for the Rx FIFOs.
When an Rx FIFO full condition is reached (RXFnS.FnPI = RXFnS.FnGI), no further
messages are written to the corresponding Rx FIFO until at least one message has been
read out and the Rx FIFO Get Index has been incremented. An Rx FIFO full condition is
signaled by RXFnS.FnF = 1. In addition interrupt flag IR.RFnF is set.
In case a message is received while the corresponding Rx FIFO is full, this message is
discarded and the message lost condition is signaled by RXFnS.RFnL = 1. In addition
interrupt flag IR.RFnL is set.
Rx FIFO Overwrite Mode
The Rx FIFO overwrite mode is configured by RXGFC.FnOM = 1.
When an Rx FIFO full condition (RXFnS.FnPI = RXFnS.FnGI) is signaled by
RXFnS.FnF = 1, the next message accepted for the FIFO overwrites the oldest FIFO
message. Put and get index are both incremented by one.
When an Rx FIFO is operated in overwrite mode and an Rx FIFO full condition is signaled,
reading of the Rx FIFO elements must start at least at get index + 1. This is because it can
happen that a received message is written to the Message RAM (put index) while the CPU
is reading from the Message RAM (get index). In this case inconsistent data may be read
from the respective Rx FIFO element. Adding an offset to the get index when reading from
the Rx FIFO avoids this problem. The offset depends on how fast the CPU accesses the Rx
FIFO.
After reading from the Rx FIFO, the number of the last element read has to be written to the
Rx FIFO Acknowledge Index RXFnA.FnA. This increments the get index to that element
number. In case the put index has not been incremented to this Rx FIFO element, the Rx
FIFO full condition is reset (RXFnS.FnF = 0).
Tx handling
The Tx Handler handles transmission requests for the Tx FIFO, and the Tx Queue. It
controls the transfer of transmit messages to the CAN core, the Put and Get Indices, and
the Tx Event FIFO.Up to three Tx Buffers can be set up for message transmission. The CAN
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