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FD controller area network (FDCAN) RM0440

1994/2126 RM0440 Rev 4

44.4.20 FDCAN extended ID and mask register (FDCAN_XIDAM)

Address offset: 0x0084

Reset value: 0x1FFF FFFF

44.4.21 FDCAN high-priority message status register (FDCAN_HPMS)

This register is updated every time a Message ID filter element configured to generate a

priority event match. This can be used to monitor the status of incoming high priority

messages and to enable fast access to these messages.

Address offset: 0x0088

Reset value: 0x0000 0000

Bit 1 RRFS: Reject remote frames standard

0: Filter remote frames with 11-bit standard IDs

1: Reject all remote frames with 11-bit standard IDs

These are protected write (P) bits, which means that write access by the bits is possible only

when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

Bit 0 RRFE: Reject remote frames extended

0: Filter remote frames with 29-bit standard IDs

1: Reject all remote frames with 29-bit standard IDs

These are protected write (P) bits, which means that write access by the bits is possible only

when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. EIDM[28:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

EIDM[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:0 EIDM[28:0]: Extended ID mask

For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the

Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the

reset value of all bits set to 1 the mask is not active.

These are protected write (P) bits, which means that write access by the bits is possible only

when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

FLST Res. Res. FIDX[4:0] MSI[1:0] Res. Res. Res. BIDX[2:0]

r rrrrrrr rrr

ST STM32G474 User Manual

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