FD controller area network (FDCAN) RM0440
1996/2126 RM0440 Rev 4
44.4.23 CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A)
Address offset: 0x0094
Reset value: 0x0000 0000
44.4.24 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S)
Address offset: 0x0098
Reset value: 0x0000 0000
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 F0FL[3:0]: Rx FIFO 0 fill level
Number of elements stored in Rx FIFO 0, range 0 to 3.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. F0AI[2:0]
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 F0AI[2:0]: Rx FIFO 0 acknowledge index
After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to
write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx
FIFO 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. RF1L F1F Res. Res. Res. Res. Res. Res. F1PI[1:0]
rr rr
1514131211109876543210
Res. Res. Res. Res. Res. Res. F1GI[1:0] Res. Res. Res. Res. F1FL[3:0]
rr rrrr
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 RF1L: Rx FIFO 1 message lost
This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset.
0: No Rx FIFO 1 message lost
1: Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0
Bit 24 F1F: Rx FIFO 1 full
0: Rx FIFO 1 not full
1: Rx FIFO 1 full
Bits 23:18 Reserved, must be kept at reset value.
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