ST STM32G474 User Manual

RM0440 Rev 4 2103/2126
RM0440 Debug support (DBG)
2112
47.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
Address: 0xE004 200C
Power on reset (POR): 0x0000 0000
System reset: not affected
Access: Only 32-bit access are supported.
47.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
Address: 0xE004 2010
Power on reset (POR): 0x0000 0000
System reset: not affected
Access: Only 32-bit access are supported.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_I
2C4_S
TOP
Res.
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DBG_I2C4_STOP: I2C4 SMBUS timeout counter stopped when core is halted
0: Same behavior as in normal mode
1: The I2C4 SMBus timeout is frozen
Bit 0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res.
DBG_
HRTIM
_STOP
Res. Res. Res. Res. Res.
DBG_
TIM20
_STOP
Res.
DBG_
TIM17_
STOP
DBG_TI
M16_ST
OP
DBG_TI
M15_ST
OP
rw rw rw rw rw
1514131211109876543 2 1 0
Res. Res.
DBG_
TIM8_
STOP
Res.
DBG_
TIM1_
STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 DBG_HRTIM_STOP: HRTIM counter stopped when core is halted
0: The clock of the HRTIM counter is fed even if the core is halted
1: The clock of the HRTIM counter is stopped when the core is halted
Bits 25:21 Reserved, must be kept at reset value.

ST STM32G474 Specifications

General

Brand	ST
Model	STM32G474
Category	Microcontrollers
Language	English