RM0440 Rev 4 371/2126
RM0440 System configuration controller (SYSCFG)
380
Table 58 describes when the bit 9 (ANASWVDD) and the bit 8 (BOOSTEN) should be set or
reset depending on the voltage settings.
Note: When FM+ mode is activated on GPIO pin, the speed configuration of the GPIO (in
GPIOx_OSPEEDR register) is ignored. Program this register only after the AF selection
through the GPIOx_AFRH or GPIOx_AFRL register.
Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.
Bit 21 I2C2_FMP: I2C2 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.
Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.
Bit 19 I2C_PB9_FMP: Fast-mode Plus (Fm+) driving capability activation on PB9
This bit enables the Fm+ driving mode for PB9.
0: PB9 pin operates in standard mode.
1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed.
Bit 18 I2C_PB8_FMP: Fast-mode Plus (Fm+) driving capability activation on PB8
This bit enables the Fm+ driving mode for PB8.
0: PB8 pin operates in standard mode.
1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed.
Bit 17 I2C_PB7_FMP: Fast-mode Plus (Fm+) driving capability activation on PB7
This bit enables the Fm+ driving mode for PB7.
0: PB7 pin operates in standard mode.
1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed.
Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6
This bit enables the Fm+ driving mode for PB6.
0: PB6 pin operates in standard mode.
1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 ANASWVDD: GPIO analog switch control voltage selection
0: I/O analog switches supplied by VDDA or booster when booster is ON
1: I/O analog switches supplied by VDD.
Refer to Tab le 5 8 for bit 9 setting.
Bit 8 BOOSTEN: I/O analog switch voltage booster enable
0: I/O analog switches are supplied by V
DDA
voltage. This is the recommended configuration
when using the ADC in high V
DDA
voltage operation.
1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V
DD
). This is
the recommended configuration when using the ADC in low V
DDA
voltage operation.
Bits 7:0 Reserved, must be kept at reset value.
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