ST STM32G474 User Manual

2126 pages

To Next Page

To Previous Page

RM0440 Rev 4 437/2126

RM0440 DMA request multiplexer (DMAMUX)

440

13.6.4 DMAMUX request generator channel x configuration register

(DMAMUX_RGxCR)

Address offset: 0x100 + 0x04 * x (x = 0 to 3)

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] GE

rw rw rw rw rw rw rw rw

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. SIG_ID[4:0]

rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)

Defines the number of DMA requests to be generated after a trigger event. The actual

number of generated DMA requests is GNBREQ +1.

Note: This field shall only be written when GE bit is disabled.

Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity

Defines the edge polarity of the selected trigger input

00: no event. I.e. none trigger detection nor generation.

01: rising edge

10: falling edge

11: rising and falling edge

Bit 16 GE: DMA request generator channel x enable

0: DMA request generator channel x disabled

1: DMA request generator channel x enabled

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 OIE: Trigger overrun interrupt enable

0: interrupt on a trigger overrun event occurrence is disabled

1: interrupt on a trigger overrun event occurrence is enabled

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 SIG_ID[4:0]: Signal identification

Selects the DMA request trigger input used for the channel x of the DMA request generator

Questions and Answers: