RM0440 Rev 4 535/2126
RM0440 Flexible static memory controller (FSMC)
571
Mode D - asynchronous access with extended address
Figure 63. Mode D read access waveforms
Table 139. FMC_BWTRx bitfields (mode C)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
accesses).
29:28 ACCMOD 0x2
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
MSv41683V1
A[25:0]
Memory transaction
NBL[x:0]
NEx
NOE
Data driven by memory
NWE
Data bus
NBLSET
HCLK
cycles
ADDSET HCLK cycles DATAST HCLK cycles DATAHLD
HCLK cycles
High
ADDHLD
HCLK
cycles
NADV
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