RM0440 Rev 4 649/2126
RM0440 Analog-to-digital converters (ADC)
724
Figure 118. Left alignment (offset enabled, signed value)
Gain compensation
When GCOMP bit is set in ADC_CFGR2 register, the gain compensation is activated on all
the converted data. After each conversion, data is calculated with the following formula.
As GCOMPCOEFF can be programmed from 0 to 16383, the actual gain compensation
factor can range from 0 to 3.999756.
Before storing the resulting data in RDATA or JDATAx registers, the LSB−1 value is
evaluated to round up the data and minimize the error.
The gain compensation is also effective for the oversampling. When the gain compensation
is used for the oversampling mode, the gain calculation is performed after the accumulation
and right-shift operations to minimize the power consumption (the gain calculation is done
only once instead of at each conversion).
Offset compensation
When SATEN bit is set in ADC_OFRy register during offset operation, data are unsigned. All
the offset data will saturate at 0x000, and when OFFSETPOS bit is set offset direction is
positive then the data will saturate at 0xFFF. (These are example of 12 bit mode). When 8
bit mode, it saturate at 0x00 and 0xFF respectively.
The analog watchdog comparison is performed on unsigned values, after offset and gain
compensation. For correct watchdog operation, the data after offset compensation must be
in unsigned format (SATEN bit set to 1 in ADC_OFRy register).
12-bit data
8-bit data
10-bit data
6-bit data
bit15 bit0bit7
bit15 bit0bit7
bit15 bit0bit7
bit15 bit0bit7
MS31018V1
0
0
0
SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
SEXT D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0
SEXT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0
0
SEXT SEXT
DATA DATA adc result()GCOMPCOEFF()4096⁄×=
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