RM0440 Rev 4 865/2126
RM0440 High-resolution timer (HRTIM)
1083
Consequently, it does not modify the auxiliary outputs in parallel with the regular outputs
going to the output stage (see Section 27.3.18 for details). They provide the following
internal status, events and signals:
– O1CPY, O2CPY, SETxy and RSTxy status flags, together with the corresponding
interrupts and DMA requests
– Capture triggers upon output set/reset (TA2, TB2, TC2, TD2, TE2, TF2)
– External event filters generated with a Tx2 output copy
For instance the SETx1 flag is related to the output 1 when SWP = 0 and is related to the
output 2 when SWPx = 1.
Similarly, the swap mode does not change the attribution of control bits in the
HRTIM_OUTxR register (DIDLx, CHPx, FAULTx[1:0], IDLESx, POLx bits). For instance, the
POL1 bit controls the output 1 polarity whatever the SWP bit value.
Note: The SWPx bits are ignored in push-pull mode (PSHPLL = 1 in the HRTIM_TIMxCR
register).
Capture
The timing unit has the capability to capture the counter value, triggered by internal and
external events. The purpose is to:
– measure events arrival timings or occurrence intervals
– update compare 2 and compare 4 values in auto-delayed mode (see
Section : Auto-
delayed mode
).
The capture is done with f
HRTIM
resolution: for a clock prescaling ratio below 32
(CKPSC[2:0] < 5), the least significant bits of the register are not significant (read as 0).
The timer has 2 capture registers: HRTIM_CPT1xR and HRTIM_CPT2xR. The capture
triggers are programmed in the HRTIM_CPT1xCR and HRTIM_CPT2xCR registers.
The capture of the timing unit counter can be triggered by up to 28 events that can be
selected simultaneously in the HRTIM_CPT1xCR and HRTIM_CPT2xCR registers, among
the following sources:
• The external events, EXTEVNT1..10 (10 events)
• All other timing units (e.g. timer B..F for timer A): compare 1, 2 and output 1 set/reset
events (16 events)
• The timing unit: update (1 event)
• A software capture (1 event)
Several events can be selected simultaneously to handle multiple capture triggers. In this
case, the concurrent trigger requests are ORed. The capture can generate an interrupt or a
DMA request when CPTxIE and CPTxDE bits are set in the HRTIM_TIMxDIER register.
Over-capture is not prevented by the circuitry: a new capture is triggered even if the
previous value was not read, or if the capture flag was not cleared.
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