RM0440 Rev 4 885/2126
RM0440 High-resolution timer (HRTIM)
1083
27.3.7 Set / reset events priorities and narrow pulses management
This section describes how the output waveform is generated when several set and/or reset
requests are occurring within 3 consecutive
t
HRTIM
periods.
Case 1: clock prescaler CKPSC[2:0] < 5
An arbitration is performed during each t
HRTIM
period, in 3 steps:
1. For each active event, the desired output transition is determined (set, reset or toggle).
2. A predefined arbitration is performed among the active events (from highest to lowest
priority CMP4
→ CMP3 → CMP2 → CMP1 → PER, see Section : Concurrent set
requests/ Concurrent reset requests).
3. A high-resolution delay-based arbitration is performed with reset having the highest
priority, among the low-resolution events and events having won the predefined
arbitration.
When set and reset requests from two different sources are simultaneous, the reset action
has the highest priority. If the interval between set and reset requests is below 2 f
HRTIM
period, the behavior depends on the time interval and on the alignment with the f
HRTIM
clock, as shown on Figure 215.
Note: If the set and reset requests are simultaneous and coming from the same timing unit, the
CMPx priority applies, as shown in step 2 here-above. For instance, taking CMP2 = CMP4:
- If CMP2 does a set and CMP4 a reset, the output is reset.
- If CMP2 does a reset and CMP4 a set, the output is set.
To Next Page
General
