5-11
IM DLM6054-01EN
Vertical and Horizontal Control
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Index
App
State Display (State)
With this feature, you can use the edges of a specified clock signal to trigger the acquisition of the
state of the input logic signal. Even if the logic signal changes, the state will not change until the next
clock edge.
• Clock signal
Y
ou can select the clock signal from bits A0 to A7, B0 to B7, and D0 to D7. (On 16-bit models, you
can select from bits A0 to A7 and C0 to C7.)
• Polarity
Select the clock edges upon which you want to detect and dis
play the logic signal state.
Rising edges
Falling edges
Rising and falling edges
Clock signal
State display
Input signal
Repetitive high-frequency pulse
Grouping (Mapping)
• You can assign logic signals from bits A0 to A7, B0 to B7, and D0 to D7 (bits A0 to A7 and C0 to C7
on 16-bit models) to Group 1 to Group 5.
• Out of the assigned logic signals, the logic signal that is closes
t to the LSB side of the Mapping
dialog box is the LSB. The assigned logic signals are arranged between the LSB and the MSB in
order from the lowest digit. When the bits are counted or displayed in hexadecimal format, they are
divided into groups of four starting from the LSB.
When the bits are counted or displayed in hexadecimal format, they are
divided into groups of four starting from the LSB. The digit containing the
MSB may not contain four bits.
Note
• You cannot assign the same bit to the same group multiple times.
• You cannot assign the same bit to multiple groups. If you assign a bit to the group that you are editing and
that bit has already been assigned to another group, the bit will be removed from its previous group.
Example for When B5 Is Deleted
All of the bits that are closer to the
LSB than the deleted bit move one
5.2 Vertical Axis Settings for Logic Input Signals
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