6-18
IM DLM6054-01EN
Level
The range is the same as that of the edge trigger level. For details, see section 6.3.
Configuring the Trigger Coupling, HF Rejection, Hysteresis, Noise Rejection,
Window Comparator, and Trigger Level Settings (Level/Coupling)
These settings are the same as the settings for the edge trigger. For details, see section 6.3.
Triggering on a Logic Signal Bit (Logic State)
Clock Source (Clock)
You can set the source to a bit from A0 to A7, B0 to B7, C0 to C7, or D0 to D7. (On 16-bit models,
you can select from bits A0 to A7 and C0 to C7.)If you do not specify a clock source, the DLM6000
just triggers on the state conditions.
Clock Source Polarity
The DLM6000 detects the clock source polarity using the thresholds (see section 5.2) that you have
set.
DLM6000 triggers on rising edges.
DLM6000 triggers on falling edges.
Note
• You cannot set a state condition for the bit that is selected as the clock source.
• When checking the state conditions in sync with the clock source, the DLM6000 may not trigger properly
if the pattern setup time or hold time for the clock source is less than 1 ns.
Setting the State Conditions for Each Bit
• Pattern
You can set the state condition for each bit to H, L, or X.
H The signal must be high.
L The signal must be low.
X No conditions have to be met (“don’t care”).
• Logic
You can set the logic for all the conditions to AND or OR.
AND The DLM6000 triggers when all the specified conditions are met.
OR The DLM6000 triggers when any of the specified conditions is met.
Setting State Conditions for Groups
• Pattern
You can specify state conditions for groups of bits in hexadecimal, binary, or symbol format.
• Hex
0 to F For information about how bits are handled when you select the hexadecimal format,
see section 5.17.
X No conditions have to be met (“don’t care”).
• Bin
0 The signal must be low.
1 The signal must be high.
X No conditions have to be met (“don’t care”).
6.6 Triggering on State Conditions
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