YOKOGAWA DL7440 User Manual

10-83
IM 701450-01E
10
Analyzing and Searching Waveforms
• Hysteresis
You can set the hysteresis on the level for detecting the synchronization clock. The
selectable range is 0.3 divisions to 4.0 divisions. The resolution is 0.1 divisions.
• When the level of the clock signal changes from below the specified lower limit of
hysteresis to above and including the upper limit of hysteresis, it is detected as a
synchronization clock.
• When the level of the clock signal changes from above the specified upper limit of
hysteresis to below and including the lower limit of hysteresis, it is detected as a
synchronization clock.
• For all other cases, it is not detected as a synchronization clock.
• Slope
You can select which slope edge, rising or falling, of the synchronization clock is to be
detected.
Rising slope
Falling slope
Data to Be Analyzed
The data that can be analyzed is the I/O data signal on the SPI Bus (Data1 and Data2).
The data in the following display range can be analyzed. Apply the Data1 and Data2
signals to CH2 and CH3.
• Waveform data that is displayed when waveform acquisition is stopped.
• History waveform data (waveform selected by Select Record on the History menu).
• Waveform data loaded from a storage medium.
Level for Determining the Status of the Data to Be Analyzed
You can set the level for determining the status of the data to be analyzed. The
selectable range is 8 divisions within the screen. The resolution is 0.01 V/div. Thr
Upper must be greater than or equal to Thr Lower.
Level for determining 1 (Thr Upper)
You can set the level for determining the status 1. When the data being analyzed exceeds
the specified level, it is determined to be 1.
Level for determining 0 (Thr Lower)
You can set the level for determining the status 0. When the data being analyzed is below
the specified level, it is determined to be 0.
Between Thr Upper and Thr Lower
The status when the data being analyzed is between the levels specified by Thr Upper and
Thr Lower (including the Thr Upper and Thr Lower values) is determined to be indefinite data.
Chip Select Signal (CS)
You can select the signals of CH4 to CH8 or logic input (A0 to A7 of Pod A) for the CS
signal on the SPI Bus. CH5 to CH8 can be used on the DL7480. The logic input is
optional.
• Level for Determining the Status of the CS Signal
When the channel signal is set to be the CS signal, you can set the level for
determining the high (H) or low (L) status of the CS signal for each channel. The
selectable range is 8 divisions within the screen. The resolution is 0.01 V/div.
• Use/Not Use as a CS Signal
You can select whether the channel is to be a CS signal (ON/OFF) for each channel
CH4 to CH8 or logic input (A0 to A7 of Pod A).
10.11 Analyzing and Searching SPI Signals

YOKOGAWA DL7440 Specifications

General

Brand	YOKOGAWA
Model	DL7440
Category	Test Equipment
Language	English