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Avaya S8700 - Page 939

Avaya S8700
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ATM-EI (Expansion Interface Circuit Pack)
Issue 1 May 2002
8-217555-233-143
ATM Board Framer Loop-Around Test (#1260)
This test is destructive.
NOTE:
This test can be run on the standby PNC only if the board is busied out.
This test places the ATM circuit pack in ATM framer loop-around mode. Once the
board receives this message, it creates a dummy virtual circuit that originates and
ends on the same board, without leaving the board. This test verifies both the
TDM path and the Packet Path. If the TDM test path passes, then the packet path
is tested. Definitions of each test path are:
The circuit (TDM) path: one of the Tone Generators sends a bit pattern
through a TDM bus time slot to the ATM framer. The pattern is converted
into ATM cells and looped back to the ATM-EI board, which converts the
cell back into the bit pattern and puts it on a pre-determined time slot. A
Tone Detector tests for the bit pattern and reports the test result. This test
verifies that a large portion of the ATM-EIs circuit paths are functioning
correctly. Figure 8-5 shows a diagram of the test.
Figure 8-5. ATM Board Framer Loop-Around Test (#1260)
Packet path: the Packet Interface circuit pack sends packet data to the
ATM framer interface, where it is mapped into ATM cells and then looped
around internally. The cells are converted back to packet data after it has
been looped. This portion of the test verifies correct operation of the
ATM-EIs packet-bus interface and a large portion of the ATM-EI's packet
paths. Figure 8-6 shows the packet switched signal path for the ATM
circuit pack.
Tone clock
Tone detector
Packet
Interface
PNC mode
ATM
framer
looped
iodftone AWF 040699
TDM bus
(PPN)
Packet bus
(PPN)
ATM
circuit
pack

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