Intel Xeon User Manual

+VCC_CPU +VCC_CPU
+VCC_CPU+VCC_CPU
+VCC_CPU
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
R
D
C
B
B
D
C
1
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LAST REVISED:
1900 Prairie City Road
Folsom, California 095630
TITLE:
Platform Apps Engineering
SHEET
03/04/02
+VCC_CPU
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1 P2
ITP32B TAP
+VCC_CPU
TDO
TDI
TDO
TDI
P1
ITP
1-2 = P0 Only
2-3 = P0 + P1
Debug
Port
TDI
TDO
P0
JP3
ITP USE DIAGRAM
Place these resistors
near J18 (Processor 0)
VREF circuits for GTL+
Place these termination
resistors at the ends of the traces.
R77
51
51
R87
ICH3_A20M_N
4,6,53
ICH3_IGNNE_N
4,6,53
4,6,80
CPU_LINT1_NMI
4,6,53
CPU_STPCLK_N
4,80
CPU1_SMI_N
6,80
CPU0_SMI_N
R1027
51 51
R1028
ICH3_INIT_N
4,6,53,66
R74
200
CPU_BPM3_N
4,6
CPU_BPM2_N
4,6
R81
51
4,6
CPU_BPM1_N
R79
51 51
R80
51
R78 R86
1%
75
4
ITP_TDO_P1
1.5K
1%
R85
ITP_TDI_P1
4
6
ITP_TDO_P0
2
3
1
JP3
ITP_TDI_P0
6
24
22
20
18
16
14
12
10
8
6
4
25
23
21
19
17
15
13
11
9
7
5
3
12
J13
0
R59
R60
00
R63
R89
0
C67
1UF1UF
C68 C65
1UF 1UF
C66
ITP_TMS_P
4,6
DBR_RESET_N
64
ITP_TRST_N
4,6
27.4
1%
R88
200
R838
R76
200
200
R75
200
R73 R72
200 200
R71 R70
200
100
1%
R61 R62
1%
49.9
CPU_BPM4_N
4,6
CPU_BPM5_N
4,6
FSB_CPURST_N
4,6,10
ITP_TCK_P
4,6,9
ITP_TCK_P
4,6,9
CPU1_GTL_VREF2 4
STPPWRITP_BCLK1
65
ITP_BCLK0
65
CPU0_GTL_VREF1 6 CPU0_GTL_VREF2 6
CPU1_GTL_VREF1 4
49.9
1%
R65R64
1%
100
R67
1%
49.9100
1%
R66
49.9
1%
R69R68
1%
100
4,6
CPU_BPM0_N
ICH3_LINT0_INTR
4,6,53
ICH3_CPUSLP_N
4,6,53
200
R1026
9

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English