© 2004 Microchip Technology Inc. DS70061C-page 14-17
Section 14. Output Compare
Output
Compare
14
14.3.2.6 Special Cases for Dual Compare Mode Generating Continuous Output Pulses
Depending on the relationship of the OCxR, OCxRS and PRy values, the output compare module
may not provide the expected results. These special cases are specified in Table 14-2, along with
the resulting behavior of the module.
Table 14-2: Special Cases for Dual Compare Mode Generating Continuous Output Pulses
SFR Logical
Relationship
Special Conditions Operation
Output
at OCx
PRy >= OCxRS and
OCxRS > OCxR
OCxR = 0
Initialize TMRy = 0
In the first iteration of the TMRy counting from 0x0000 up
to PRy, the OCx pin remains low, no pulse is generated.
After the TMRy resets to zero (on period match), the OCx
pin goes high. Upon the next TMRy to OCxRS match, the
OCx pin goes low. If OCxR = 0 and PRy = OCxRS, the pin
will remain low for one clock cycle, then be driven high
until the next TMRy to OCxRS match. The OCxIF bit will
be set as a result of the second compare.
There are two alternative initial conditions to consider:
a] Initialize TMRy = 0 and set OCxR >= 1
b] Initialize TMRy = PRy (PRy > 0) and set OCxR = 0
Continuous pulses with
the first pulse delayed
by the value in the PRy
register, depending on
setup.
PRy >= OCxR and
OCxR >= OCxRS
OCxR >= 1 and
PRy >= 1
TMRy counts up to OCxR and on a compare match event
(i.e., TMRy = OCxR), the OCx pin is driven to a high state.
TMRy then continues to count and eventually resets on
period match (i.e., PRy =TMRy). The timer then restarts
from 0x0000 and counts up to OCxRS, and on a compare
match event (i.e., TMRy = OCxR), the OCx pin is driven to
a low state. The OCxIF bit will be set as a result of the
second compare.
Continuous pulses
OCxRS > PRy and
PRy >= OCxR
None Only one transition will be generated at the OCx pin until
the OCxRS register contents have been changed to a
value less than or equal to the period register contents
(PRy). OCxIF is not set until then.
Rising edge/
transition to high
OCxR = OCxRS =
PRy = 0x0000
None Continuous output pulses are generated at the OCx pin.
The first pulse is delayed 2 instruction clock periods upon
the match of the timer and period register. The OCxIF bit
will be set as a result of the second compare.
First pulse is delayed.
Continuous pulses
are generated.
OCxR > PRy None Unsupported mode, Timer resets prior to match condition. Remains low
Note 1: In all the cases considered herein, the TMRy register is assumed to be initialized to 0x0000.
2: OCxR = Compare Register, OCxRS = Secondary Compare Register, TMRy = Timery Count,
PRy = Timery Period Register.
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