Microchip Technology dsPIC30F - Page 300

dsPIC30F Family Reference Manual
DS70061C-page 14-18 © 2004 Microchip Technology Inc.
14.3.3 Pulse Width Modulation Mode
When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘110’ or ‘111’, the selected output
compare channel is configured for the PWM (Pulse Width Modulation) mode of operation.
The following two PWM modes are available:
• PWM without Fault Protection Input
• PWM with Fault Protection Input
The OCFA or OCFB Fault input pin is utilized for the second PWM mode. In this mode, an
asynchronous logic level ‘0’ on the OCFx pin will cause the selected PWM channel to be
shutdown. (Described in Section 14.3.3.1, “PWM with Fault Protection Input Pin”.)
In PWM mode, the OCxR register is a read only slave duty cycle register and OCxRS is a buffer
register that is written by the user to update the PWM duty cycle. On every timer to period register
match event (end of PWM period), the duty cycle register, OCxR, is loaded with the contents of
OCxRS. The TyIF interrupt flag is asserted at each PWM period boundary.
The following steps should be taken when configuring the output compare module for PWM
operation:
1. Set the PWM period by writing to the selected timer period register (PRy).
2. Set the PWM duty cycle by writing to the OCxRS register.
3. Write the OxCR register with the initial duty cycle.
4. Enable interrupts, if required, for the timer and output compare modules. The output
compare interrupt is required for PWM Fault pin utilization.
5. Configure the output compare module for one of two PWM Operation modes by writing to
the Output Compare mode bits OCM<2:0> (OCxCON<2:0>).
6. Set the TMRy prescale value and enable the time base by setting TON (TxCON<15>) = 1.
An example PWM output waveform is shown in Figure 14-10.
Figure 14-10: PWM Output Waveform
Note: The OCxR register should be initialized before the Output Compare module is first
enabled. The OCxR register becomes a read only duty cycle register when the
module is operated in the PWM modes. The value held in OCxR will become the
PWM duty cycle for the first PWM period. The contents of the duty cycle buffer
register, OCxRS, will not be transferred into OCxR until a time base period match
occurs.
Period = (PRy + 1)
Duty Cycle = (OCxRS )
Timery is cleared and new duty cycle value is loaded from OCxRS into OCxR.
Timer value equals value in the OCxR register, OCx Pin is driven low.
Timer overflow, value from OCxRS is loaded into OCxR, OCx pin driven high.
21
3
2
3
1
TyIF interrupt flag is asserted.