© 2004 Microchip Technology Inc. DS70074C-page 26-5
Section 26. Appendix
Appendix
26
A.3 Transfer Acknowledge
All data must be transmitted per byte, with no limit to the number of bytes transmitted per data
transfer. After each byte, the slave-receiver generates an Acknowledge bit (ACK
) (Figure A-4).
When a slave-receiver doesn’t acknowledge the slave address or received data, the master
must abort the transfer. The slave must leave SDA high so that the master can generate the
Stop condition (Figure A-1).
Figure A-4: Slave-Receiver Acknowledge
If the master is receiving the data (master-receiver), it generates an Acknowledge signal for
each received byte of data, except for the last byte. To signal the end of data to the
slave-transmitter, the master does not generate an acknowledge (not acknowledge). The slave
then releases the SDA line so the master can generate the Stop condition. The master can also
generate the Stop condition during the Acknowledge pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next byte, holding the SCL line low will force
the master into a wait state. Data transfer continues when the slave releases the SCL line. This
allows the slave to move the received data or fetch the data it needs to transfer before allowing
the clock to start. This wait state technique can also be implemented at the bit level, Figure A-5.
Figure A-5: Data Transfer Wait State
S
Data
Output by
Transmitter
Data
Output by
Receiver
SCL from
Master
Clock Pulse for
Acknowledgment
not acknowledge
acknowledge
1
2
8
9
Start
Condition
12 78 9 123 • 89
P
SDA
SCL
S
Start
Condition
Address R/W
ACK Wait
State
Data ACK
MSb Acknowledgment
Signal from Receiver
Acknowledgment
Signal from Receiver
Byte Complete
Interrupt with Receiver
Clock Line Held Low while
Interrupts are Serviced
Stop
Condition
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