Embedded Flash memory (FLASH) for category 3 devices RM0440
106/2126 RM0440 Rev 4
In fast programming: all the data must be written successively. MISSERR is set if the
previous data programmation is finished and the next data to program is not written yet.
• FASTERR: Fast Programming Error
In fast programming: FASTERR is set if one of the following conditions occurs:
– When FSTPG bit is set for more than 7ms which generates a time-out detection.
– When the fast programming has been interrupted by a MISSERR, PGAERR,
WRPERR or SIZERR.
If an error occurs during a program or erase operation, one of the following error flags is set
in the FLASH_SR register:
PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (Program error flags),
WRPERR (Protection error flag)
In this case, if the error interrupt enable bit ERRIE is set in the Flash status register
(FLASH_SR), an interrupt is generated and the operation error flag OPERR is set in the
FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Programming and caches
If a Flash memory write access concerns some data in the data cache, the Flash write
access modifies the data in the Flash memory and the data in the cache.
If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the Flash access control register (FLASH_ACR).
Note: The I/D cache should be flushed only when it is disabled (I/DCEN = 0).
3.3.8 Read-while-write (RWW) available only in dual bank mode
(DBANK=1)
The dual bank mode is available only when the DBANK option bit is set, allowing read-
while-write operations. This feature allows to perform a read operation from one bank while
an erase or program operation is performed to the other bank.
Note: Write-while-write operations are not allowed. As an example, It is not possible to perform an
erase operation on one bank while programming the other one.
Read from bank 1 while page erasing in bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a page erase
operation on bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash
status register (FLASH_SR) (BSY is active when erase/program operation is on going
in bank 1 or bank 2).
2. Set PER bit, PSB to select the page and BKER to select the bank in the Flash control
register (FLASH_CR).
3. Set the STRT bit in the FLASH_CR register.
4. Wait for the BSY bit to be cleared (or use the EOP interrupt).
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